Classify each of the below situations as either a structural hazard, control hazard, or a data hazard:

a. The memory shared by instruction fetches and data accesses in a von Neumann memory architecture. This is a __.

b. A conditional branch instruction in a RISC processor. This is a ___.

c. An integer multiplier that takes two cycles to complete when all other arithmetic operations in a processor take one cycle. Assume that there are sufficient register read and write ports to support all the necessary reads and writes per cycle. This is a ___.

A. This is a structural hazard.

B. This is a control hazard.

C. This is a data hazard.

Explanation:

There are various types of hazards that occur in computer architecture based on certain conditions. The memory shared by instruction fetches and data accesses in a Von Neumann memory architecture. This is a structural hazard. A conditional branch instruction in a RISC processor. This is a control hazard.

An integer multiplier that takes two cycles to complete when all other arithmetic operations in a processor take one cycle. Assume that there are sufficient register read and write ports to support all the necessary read and writes per cycle. This is a data hazard.

Data hazards occur happen when the pipeline changes the request for perusing/composing gets to operands with the goal that the request varies from the request seen by consecutively executing guidelines on the unpipelined machine.

A structural hazard occurs when a piece of the processor's equipment is required by at least two guidelines simultaneously.

Control hazards can cause a more noteworthy presentation misfortune for the DLX pipeline than data hazards.