Discuss how analysis might be used to design "clock

The answer to this question can be given as:

For design clock the analysis might use the process of static timing analysis.

Explanation:

STA is a static timing analysis, It is the process measuring scheduled timing of digital circuit without needing simulation. It is highly performed of the combined circuits which must be traditionally designated with clock rhythm on work. Measuring this capacity of the circuit to the work at particularized speed and it needs a capacity to measure, throughout the design process, its pause at the various steps. Further, delay forethought must be consolidated into the internal loop of timing optimizer at several stages of design, such as logic organization, layout (placement and routing), optimizations acted late in the map cycle. While such timing measures can be achieved using these circuit simulation, such that it is an approach which is liable and is too slow to practical. It plays a vital role in facilitating the quick and reasonably accurate measure of circuit timing. The speedup surfaces due to the use of simplified delay models, and because of its ability to examine the effects of logical interactions within signs is checked. Nonetheless, it has become a backbone of design overhead the last some decades. When there is no action at a list.