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31 August, 10:28

n the first circuit configuration (RL = 10k), how many periods of the input signal V1 does it take for the output voltage, V3, to reach a final periodic state? Choose the option closest to the value you measure.

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  1. 31 August, 10:40
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    For RL = 10k, measure the voltage of the capacitor at one half of the period (take the origin of time at the start of the first positive swing of the input signal)
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